In a high-speed serializer/deserialzer (SerDes), data is sent without a common clock between transmitter and receiver. In the presence of jitter, both the phase and the frequency of an analog-digital converter (ADC) sampling clock at a near-end receiver deviate from a reference clock. Timing recovery, also known as clock recovery, is used in clock and data recovery (CDR) to track the phase and frequency of an incoming signal and provide either timing or clock for data recovery.
It is well known that timing recovery suffers from the latency of the timing recovery loop. In synchronous timing recovery, or alternatively, a digital phase-locked loop (PLL), the phase and frequency of an ADC sampling clock are adjusted to lock to the phase of the incoming signal. In asynchronous timing recovery, the recovered phase is used to extract the transmitted symbol from an oversampled incoming signal. In both cases, the recovered phase lags behind the phase and frequency variations of the incoming signal. This delay causes intrinsic jitter of the timing recovery circuit. Most importantly, it has significant impact on the performance of CDR which must meet a jitter tolerance (JTOL) mask.
A JTOL mask specifies the minimum jitter amplitude at frequencies of interest that a CDR needs to tolerate. The corner frequency on the JTOL mask specifies the minimum bandwidth of timing recovery loop which determines the minimum jitter frequency that a timing recovery circuit needs to track. An increase of loop latency decreases the phase margin and stability region of timing recovery loop and, accordingly, reduces loop bandwidth and JTOL.
FIG. 1 illustrates the amplitude response of a jitter transfer function (JTF). Large latency of the timing recovery loop leads to narrow loop bandwidth. Accordingly, the maximum jitter frequency that a timing recovery circuit can track is reduced.
FIG. 2 illustrates the impact of loop latency on jitter tolerance. As shown in FIG. 2, large loop latency leads to small jitter attenuation at low jitter frequencies and excessive amplification at high frequencies and, thus, degrades JTOL. The loop latency affects not only the performance of timing recovery, but also the cost and power consumption of a device.
Given the latency budget of a timing recovery loop, it is not feasible to insert additional delay stages into critical paths to ease timing closure. Low-speed cells with less leakage power are replaced with high-speed cells in order to meet the set-up and hold time of flip-flops. The resulting device can be less power-efficient and less cost-effective.
In modern multi-GHz SerDes, complex control and arithmetic logic are widely used in loop filters. Additional delay stages are inserted in a loop filter in order to meet the setup and hold time of flip-flops. The processing delay of loop filtering accounts for a significant portion of the overall latency of a timing recovery loop. A known simplified second-order digital loop filter with additional delay stages is depicted in FIG. 3.
FIG. 3 illustrates a digital loop filter 10 with additional pipeline delay stages. The filter 10 in FIG. 3 comprises a proportional control path 20 with additional a delay stages 22, an integral control path 30 with additional c delay stages 32, and a phase computation block 40 with additional b delay stages 42. The proportional control path 20 scales the phase error, i.e., e(k), detected by a phase error detector, with proportional gain Gp. It tracks the phase variation of the incoming signal.
A first integrator 34 in the integral control path 30 tracks the frequency of the incoming signal based on a received integral control gain Gi. The outputs of the proportional control path and the integral path are combined to form a phase correction signal. A second integrator 44 in the phase computation block 40 is used in computing the recovered phase θ(k) which is used to either adjust a near-end sampling clock or control the timing of data recovery.
As can be seen in FIG. 3, the recovered phase θ(k) at the output of the phase computation block 40 lags behind the detected phase error e(k). The corresponding processing delays of phase tracking and frequency tracking are (a+b) and (c+b) clock cycles, respectively.
It is desirable to reduce or eliminate the processing delay of loop filtering and accelerate the tracking of phase and frequency variations.